Generally, a computer system includes a power supply apparatus for providing stable DC voltages, e.g. 12V or 5V, required to power specified hardware components of the computer system. Since the magnitude of the CPU core voltage is different from the DC voltages offered by the power supply apparatus, an additional voltage regulator (VR) is provided on the motherboard. By the voltage regulator, a relatively higher DC voltage (e.g. 12V) is decreased to the CPU core voltage (e.g. 1.3V). Such a voltage regulator is also referred as a buck DC/DC converter.
FIG. 1 is a schematic circuit diagram illustrating a single-phase voltage regulator mounted on a motherboard according to the prior art. The single-phase voltage regulator principally comprises a PWM (pulse width modulation) control unit 10, a driver unit 20 and a power stage circuit 30. The PWM control unit 10 can issue a PWM (pulse width modulation) signal to the driver unit 20.
The driver unit 20 comprises a steering logic circuit 22 and two driving circuits 24 and 26. In response to the PWM signal, the steering logic circuit 22 issues a first steering signal and a second steering signal to the driving circuits 24 and 26, respectively. When the first steering signal and the second steering signal are received, the driving circuits 24 and 26 generate a first driving signal S1 and a second driving signal S2, respectively.
The power stage circuit 30 comprises an upper power FET (field effect transistor) M1, a lower power FET M2, an output inductor L, a current sense resistor Rs and an output capacitor Co. The drain electrode (D) of the upper power FET M1 is connected to a supply voltage Vcc. The gate electrode (G) of the upper power FET M1 is connected to the driving circuit 24 for receiving the first driving signal S1. The source electrode (S) of the upper power FET M1 is connected to a first terminal of the output inductor L. The drain electrode (D) of the lower power FET M2 is connected to the first terminal of the output inductor L. The gate electrode (G) of the lower power FET M2 is connected to the driving circuit 26 for receiving the second driving signal S2. The source electrode (S) of the lower power FET M2 is connected to the ground terminal (GND). The current sense resistor Rs is interconnected between a second terminal of the output inductor L and the output terminal Vcore of the CPU core voltage. The output capacitor Co is interconnected between the output terminal Vcore of the CPU core voltage and the ground terminal (GND).
In addition, the output terminal Vcore of the CPU core voltage is connected to a power layer (not shown) of the motherboard. The power layer is also connected to a central processing unit (CPU) for offering a desired CPU core voltage to the CPU. The upper power FET M1 and the lower power FET M2 are N-type MOSFETs. The supply voltage Vcc is 12V.
In response to the first driving signal S1 and the second driving signal S2, the power FETs M1 and M2 are conducted such that an output current Io flows to the CPU through the output inductor L and the current sense resistor Rs. According to the magnitude of the output current Io, it is realized whether the CPU is operated at a heavy load or at a light load. Moreover, a feedback logic circuit 12 of the PWM control unit 10 are connected to both ends of the current sense resistor Rs to detect the potential difference across the both ends of the current sense resistor Rs. The potential difference across the both ends of the current sense resistor Rs is also referred as a sensing voltage Vs. In a case that the CPU is operated at a heavy load, the feedback logic circuit 12 of the PWM control unit 10 will increase the pulse width of the PWM signal according to the sensing voltage Vs, thereby increasing the output current Io. Whereas, in another case that the CPU is operated at a light load, the feedback logic circuit 12 of the PWM control unit 10 will decrease the pulse width of the PWM signal according to the sensing voltage Vs, thereby reducing the output current Io.
Recently, as the operating frequency of the CPU is gradually increased, the watts of the power required for operating the CPU need to be correspondingly increased. Under this circumstance, the conventional single-phase voltage regulator fails to provide sufficient output current to the CPU. For solving this problem, a multi-phase voltage regulator is provided on the motherboard to offer desired output current to the CPU.
FIG. 2A is a schematic circuit block diagram illustrating a four-phase voltage regulator mounted on a motherboard according to the prior art. As shown in FIG. 2A, the four-phase voltage regulator principally comprises a PWM (pulse width modulation) control unit 40, a first driver unit 50, a second driver unit 60, a third driver unit 70, a fourth driver unit 80, a first power stage circuit 90, a second power stage circuit 100, a third power stage circuit 110 and a fourth power stage circuit 120. The PWM control unit 40 can issue four pulse signals PWM1, PWM2, PWM3 and PWM4 to the first driver unit 50, the second driver unit 60, the third driver unit 70 and the fourth driver unit 80, respectively. The first driver unit 50 is connected to the first power stage circuit 90. The second driver unit 60 is connected to the second power stage circuit 100. The third driver unit 70 is connected to the third power stage circuit 110. The fourth driver unit 80 is connected to the fourth power stage circuit 120. In addition, the output terminals Vcore of the CPU core voltages that are outputted from the four power stage circuit 90, 100, 110 and 120 are all connected to a power layer (not shown) of the motherboard. The power layer is also connected to the CPU for offering a desired CPU core voltage to the CPU. In other words, the output current to be transmitted to the CPU is offered by the four-phase voltage regulator according to the four pulse signals PWM1, PWM2, PWM3 and PWM4. The configurations and the operating principles of the driver units 50, 60, 70 and 80 are identical to those of the driver unit 20 shown in FIG. 1, and are not redundantly described herein. The configurations and the operating principles of the power stage circuits 90, 100, 110 and 120 are identical to those of the power stage circuit shown in FIG. 1, and are not redundantly described herein.
When the first pulse signal PWM1 is received by the first driver unit 50, the first driver unit 50 issues a first driving signal S11 and a second driving signal S12 to the first power stage circuit 90. In response to the first driving signal S11 and the second driving signal S12, the first power stage circuit 90 generates a first output current Io1. In addition, a first sensing voltage Vs1 is transmitted from the first power stage circuit 90 to the feedback logic circuit 42 of the PWM control unit 40 to adjust the pulse width of the first pulse signal PWM1 as well as the magnitude of the first output current Io1. When the second pulse signal PWM2 is received by the second driver unit 60, the second driver unit 60 issues a first driving signal S21 and a second driving signal S22 to the second power stage circuit 100. In response to the first driving signal S21 and the second driving signal S22, the second power stage circuit 100 generates a second output current Io2. In addition, a second sensing voltage Vs2 is transmitted from the second power stage circuit 100 to the feedback logic circuit 42 of the PWM control unit 40 to adjust the pulse width of the second pulse signal PWM2 as well as the magnitude of the second output current Io2.
When the third pulse signal PWM3 is received by the third driver unit 70, the third driver unit 70 issues a first driving signal S31 and a second driving signal S32 to the third power stage circuit 110. In response to the first driving signal S31 and the second driving signal S32, the third power stage circuit 110 generates a third output current Io3. In addition, a third sensing voltage Vs3 is transmitted from the third power stage circuit 110 to the feedback logic circuit 42 of the PWM control unit 40 to adjust the pulse width of the third pulse signal PWM3 as well as the magnitude of the third output current Io3. When the fourth pulse signal PWM4 is received by the fourth driver unit 80, the third driver unit 80 issues a first driving signal S41 and a second driving signal S42 to the fourth power stage circuit 120. In response to the first driving signal S41 and the second driving signal S42, the fourth power stage circuit 120 generates a fourth output current Io4. In addition, a fourth sensing voltage Vs4 is transmitted from the fourth power stage circuit 120 to the feedback logic circuit 42 of the PWM control unit 40 to adjust the pulse width of the fourth pulse signal PWM4 as well as the magnitude of the fourth output current Io4.
FIG. 2B is a schematic timing waveform diagram illustrating related signals processed in the four-phase voltage regulator shown in FIG. 2A. The PWM control unit 40 successively issues the first pulse signal PWM1, the second pulse signal PWM2, the third pulse signal PWM3 and the fourth pulse signal PWM4 in a cycle period T. In addition, each cycle period T may be evenly divided into four time segments including a first time segment t1, a second time segment t2, a third time segment t3 and a fourth time segment t4. As shown in FIG. 2B, during the first time segment t1, the first pulse signal PWM1 is at a high-level state and thus the first sensing voltage Vs1 is employed to adjust the pulse width of the first pulse signal PWM1. Likewise, during the second time segment t2, the second pulse signal PWM2 is at a high-level state and thus the second sensing voltage Vs2 is employed to adjust the pulse width of the second pulse signal PWM2. Likewise, during the third time segment t3, the third pulse signal PWM3 is at a high-level state and thus the third sensing voltage Vs3 is employed to adjust the pulse width of the third pulse signal PWM3. Likewise, during the fourth time segment t4, the fourth pulse signal PWM4 is at a high-level state and thus the fourth sensing voltage Vs4 is employed to adjust the pulse width of the fourth pulse signal PWM4.
Since the phase number of the multi-phase voltage regulator has been previously determined according to the manufacturers' design, the PWM control unit 40 can provide a fixed number of pulse signals. Recently, for enhancing the performance of a computer system, the hobby user may implement an overclocking function or an overvolting function to operate the CPU at its optimal performance. In a case that the overclocking or overvolting function is implemented at a fixed phase number of the multi-phase voltage regulator, some drawbacks possibly occur. The drawbacks include for example the reduced efficiency of the multi-phase voltage regulator, the generation of much heat, burning of the power FETs and/or the breakdown of the output capacitors.